Field effect transistors (FETs) are the basic building block of today's integrated circuits (ICs). Such transistors can be formed in conventional bulk semiconductor substrates (such as silicon) or in an SOI layer of a silicon-on-insulator (SOI) substrate.
In order to be able to make ICs, such as memory, logic, and other devices, of higher integration density than currently feasible, one has to find ways to further downscale the dimensions of field effect transistors (FETs), such as metal-oxide-semiconductor field effect transistors (MOSFETs) and complementary metal oxide semiconductors (CMOS). Scaling achieves compactness and improves operating performance in devices by shrinking the overall dimensions and operating voltages of the device, while maintaining the device's electrical properties. Additionally, all dimensions of the device must be scaled simultaneously in order to optimize the devices' electrical performance.
The scaling of the physical processes breaks down when new phenomena, which are typically absent in the larger structures, dominate the devices behavior. For example, on decreasing the size of a MOSFET, at some point the channel length approaches the depletion layer widths of the source and drain. This results in a degradation of the subthreshold characteristics of the device and a failure to achieve current saturation, which ultimately reduces control of the gate. This phenomenon is called the “short-channel effect”. Short-channel effects are well known to those skilled in the art as the decrease in threshold voltage, Vt, in short-channel devices, i.e., sub-0.1 μm due to two dimensional electrostatic charge sharing between the gate and the source/drain regions. One can suppress the short-channel effect by highly doping the channel, at the expense of reduced mobility, lower operating speed and increased risk for avalanches at the drain.
Prior attempts to improve short-channel effects include forming retrograded wells by implanting a high concentration of counter-dopant at the channel and source/drain extensions. The high concentration of counter-dopant at the PN junctions (source/channel interface, channel/drain interface) of the device disadvantageously result in increased device leakage.
In view of the state of the art mentioned above, it would be highly desirable to provide MOSFETS having gate lengths on the order of about 10 nm or less, which overcome the above-described disadvantages.